- Low latency hardware-accelerated dynamic memory manager for hard real…
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Low latency hardware-accelerated dynamic memory manager for hard real-time and mixed-criticality systems

  1. Title statementLow latency hardware-accelerated dynamic memory manager for hard real-time and mixed-criticality systems / aut. Lukáš Kohútka, Lukáš Nagy, Viera Stopjaková
    Main entry-name Kohútka, Lukáš, 1991- (Author) - FEI Ústav elektroniky a fotoniky
    Another responsib. Nagy, Lukáš, 1985- Z2 (Author) - FEI Ústav elektroniky a fotoniky
    Stopjaková, Viera, 1968- Z1 (Author) - FEI Ústav elektroniky a fotoniky
    In DDECS 2019 / IEEE International symposium on design and diagnostics of electronic circuits and systems (DDECS 2019). -- Danvers : IEEE, 2019. -- ISBN 978-1-7281-0072-2. -- ISSN 2473-2117. -- USB, [6] s.
    Subj. Headings low latency
    real-time
    ASIC
    worst-fit
    memory allocation
    LanguageEnglish
    URLhttps://ieeexplore.ieee.org/document/8724659
    Document kindRZB - článok zo zborníka
    CategoryAFC - Reports at international scientific conferences
    Category (from 2022)V2 - Vedecký výstup publikačnej činnosti ako časť editovanej knihy alebo zborníka
    Year2019
    article

    article

Number of the records: 1  

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