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Low latency hardware-accelerated dynamic memory manager for hard real-time and mixed-criticality systems
Title statement Low latency hardware-accelerated dynamic memory manager for hard real-time and mixed-criticality systems / aut. Lukáš Kohútka, Lukáš Nagy, Viera Stopjaková Main entry-name Kohútka, Lukáš, 1991- (Author) - FEI Ústav elektroniky a fotoniky Another responsib. Nagy, Lukáš, 1985- Z2 (Author) - FEI Ústav elektroniky a fotoniky Stopjaková, Viera, 1968- Z1 (Author) - FEI Ústav elektroniky a fotoniky In DDECS 2019 / IEEE International symposium on design and diagnostics of electronic circuits and systems (DDECS 2019). -- Danvers : IEEE, 2019. -- ISBN 978-1-7281-0072-2. -- ISSN 2473-2117. -- USB, [6] s. Subj. Headings low latency real-time ASIC worst-fit memory allocation Language English URL https://ieeexplore.ieee.org/document/8724659 Document kind RZB - článok zo zborníka Category AFC - Reports at international scientific conferences Category (from 2022) V2 - Vedecký výstup publikačnej činnosti ako časť editovanej knihy alebo zborníka WOS: 000492839800023 Year 2019 article
Number of the records: 1