- Histogram memory reduction in FPGA gradient edge detectors
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Histogram memory reduction in FPGA gradient edge detectors

  1. Title statementHistogram memory reduction in FPGA gradient edge detectors / aut. Miroslav Hagara, Oldřich Ondráček, Viera Stopjaková, Radovan Stojanović
    Main entry-name Hagara, Miroslav, 1961- (Author) - FEI Ústav elektroniky a fotoniky
    Another responsib. Ondráček, Oldřich, 1950- Z1 (Author) - FEI Ústav elektroniky a fotoniky
    Stopjaková, Viera, 1968- Z1 (Author) - FEI Ústav elektroniky a fotoniky
    Stojanović, Radovan (Author)
    Translated titleRedukcia pamäte histogramu v detektoroch gradientových hrán FPGA
    In MECO 2022 / Mediterranean Conference on Embedded Computing (MECO 2022). -- Piscataway : IEEE, 2022. -- ISBN 978-1-6654-6828-2. -- ISSN 2637-9511. -- S. 375-378
    Subj. Headings edge detection
    histogram
    thresholding
    FPGA
    LanguageEnglish
    URLhttps://ieeexplore.ieee.org/document/9797154
    Document kindRZB - článok zo zborníka
    CategoryAFC - Reports at international scientific conferences
    Category (from 2022)V2 - Vedecký výstup publikačnej činnosti ako časť editovanej knihy alebo zborníka
    Type of documentpríspevok z podujatia
    In databases
    Year2022
    article

    article

Number of the records: 1  

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