- Hierarchical defect-oriented fault simulation for digital circuits
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Hierarchical defect-oriented fault simulation for digital circuits

  1. BLYZNIUK, M. et al. Hierarchical defect-oriented fault simulation for digital circuits. In IEEE European Test Workshop 2000 : proceedings. 23-26 May 2000, Cascais, Portugal. Los Alamitos : IEEE Computer Society, 2000, s.69-74. ISBN 0-7695-0701-8. I*BLY
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