FPGA implementation of histogram-based thresholding

Number of the records: 1

Title statement	FPGA implementation of histogram-based thresholding / aut. Miroslav Hagara, Peter Kubinec, Alexander Šatka, Radovan Stojanović
Main entry-name	Hagara, Miroslav, 1961- (Author) - FEI Ústav elektroniky a fotoniky
Another responsib.	Kubinec, Peter, 1966- Z1 (Author) - FEI Ústav elektroniky a fotoniky
	Šatka, Alexander, 1960- Z1 (Author) - FEI Ústav elektroniky a fotoniky
	Stojanović, Radovan (Author)
Translated title	FPGA implementácia prahovania na základe histogramu
In	MECO 2022 / Mediterranean Conference on Embedded Computing (MECO 2022). -- Piscataway : IEEE, 2022. -- ISBN 978-1-6654-6828-2. -- ISSN 2637-9511. -- S. 313-316
Subj. Headings	Otsu thresholding
	edge detection
	segmentation
	FPGA
Language	English
URL	https://ieeexplore.ieee.org/document/9797132
Document kind	RZB - článok zo zborníka
Category	AFC - Reports at international scientific conferences
Category (from 2022)	V2 - Vedecký výstup publikačnej činnosti ako časť editovanej knihy alebo zborníka
Type of document	príspevok z podujatia
In databases
Year	2022

article

citace PRO

Number of the records: 1