Number of the records: 1
FPGA implementation of histogram-based thresholding
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$2 SCOPUS $a 2-s2.0-85133971151 024 7-
$2 WOS $a 000855969800063 024 7-
$2 IEEE $a 9797132 024 7-
$2 DOI $a 10.1109/MECO55406.2022.9797132 035 $a biblio/509311 $2 CREPC2 040 $a STU $b slo 041 0-
$a eng 100 1-
$7 stu_us_auth*stu20391 $a Hagara, Miroslav, $d 1961- $u 033000 $4 aut $r Z1 $9 75 $U FEI Fakulta elektrotechniky a informatiky $T FEI Ústav elektroniky a fotoniky $X 1914 $U E030 $Y 549 242 01
$a FPGA implementácia prahovania na základe histogramu $y slo 245 10
$a FPGA implementation of histogram-based thresholding / $c aut. Miroslav Hagara, Peter Kubinec, Alexander Šatka, Radovan Stojanović 650 04
$7 stu_us_auth*0104845 $a Otsu thresholding 650 04
$7 stu_us_auth*0013143 $a edge detection 650 04
$7 stu_us_auth*stus31970 $a segmentation 650 04
$7 stu_us_auth*stus423 $a FPGA 700 1-
$7 stu_us_auth*stu9245 $a Kubinec, Peter, $d 1966- $u 033000 $r Z1 $4 aut $9 5 $U FEI Fakulta elektrotechniky a informatiky $T FEI Ústav elektroniky a fotoniky $X 2052 $U E030 $Y 549 700 1-
$7 stu_us_auth*stu9834 $a Šatka, Alexander, $d 1960- $u 033000 $r Z1 $4 aut $9 15 $U FEI Fakulta elektrotechniky a informatiky $T FEI Ústav elektroniky a fotoniky $X 1865 $U E030 $Y 549 700 1-
$7 stu_us_auth*stu143041 $a Stojanović, Radovan $4 aut $9 5 773 0-
$w stu_us_cat*0096252 $t MECO 2022 $x 2637-9511 $z 978-1-6654-6828-2 $7 m2am $a Mediterranean Conference on Embedded Computing (MECO 2022) $d Piscataway : IEEE, 2022 $g S. 313-316 856 4-
$u https://ieeexplore.ieee.org/document/9797132
Number of the records: 1