1. FIR filter synthesis algorithms for minimizing the delay and the number of adders
Title information : FIR filter synthesis algorithms for minimizing the delay and the number of adders
Variant heading : \q12*stu_us_auth*1 stu79106 \q \q1013 stu_us_auth*stu79106 \d Kang H.J. \q
%continue : \q12*stu_us_auth*1 stu79105 \q \q1013 stu_us_auth*stu79105 \d Park I.C. \q
In : \q12**1 stu169176 \q
%continue : IEEE Transactions on Circuits and Systems II-Analog and Digital Signal Processing
%continue : . Vol. 48 (2001), s.770-777, Iss.8
Document kind : článok z periodika
References : \q2479**1 stu_us_cat*stu169179*xcla \q (1) - článok