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Hierarchical test generation for combinational circuits with real defects coverage
Údaje o názve Hierarchical test generation for combinational circuits with real defects coverage Záhlavie-meno Cibáková, T. (Autor) Ďal.zodpovednosť Fischerová, M. (Autor) Gramatová, Elena, 1948- (Autor) - FIIT Ústav počítačového inžinierstva a aplikovanej informatiky Kuzmicz, W. (Autor) Pleskacz, W.A. (Autor) Raik, J. (Autor) Ubar, Raimund (Autor) Prekl.náz Hierarchické generovanie testov pre kombinančné obvody s pokrytím reálnych defektov In Microelectronics Reliability. -- Vol. 42, Iss. 7 (2002), s.1141-1149 Predmet.heslá defekty digitálny obvod generovanie testov Jazyk dok. angličtina Druh dok. RBX - článok z periodika Kategória ADC - Vedecké práce v zahraničných karentovaných časopisoch Ohlasy [1] 2006: SHANG, Q.-H. - WU, L.-H. - XIANG, F.-J. Structure-based multi-fault test generation algorithm for combinational circuit. In Journal of Harbin Institute of Technology (New Series), 2006, vol. 13, iss. 4, s.452-454. V databáze: SCOPUS. [1] c2008: WIELGUS, A. - PLESKACZ, W.A. Characterization of CMOS sequential standard cells for defect based voltage testing. [S. l.] : IEEE, c2008In EWDTS'08 : Proceedings of IEEE East-West Design and Test Symposium, Lviv; Ukraine; 9 October 2008 through 12 October 2008, s.49-54. ISBN 978-142443403-9. V databáze: SCOPUS. [1] 2012: WIELGUS, A. - POTRYKUS, B. Resistive shorts characterization in CMOS standard cells for test pattern generation. [S. l.] : SPIE - The International Society for Optical Engineering, 2012In ELTE 2013 : 11th Conference on Electron Technology, Ryn; Poland; 16 April 2012 through 20 April 2012, s.[article number: 89020W]. ISBN 978-081949521-1. V databáze: WOS ; SCOPUS. [1] 2004: UBAR, R. - AARNA, M. - KRUUS, H. - RAIK, J. How to generate high quality tests for digital systems. [New York] : IEEE, 2004In 2004 International semiconductor conference : proceedings. 27th International Semiconductor Conference (CAS), Oct 04-06, 2004, Sinaia, Romania, s.459-462. ISBN 0-7803-8499-7. V databáze: WOS. [1] 2013: KRENZ-BAATH, R. - GLOWATZ, A. - HAPKE, F. Fault collapsing of multi-conditional faults. Piscataway : IEEE, 2013In DDECS 2013 [elektronický dokument] : 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, April 8-10, 2013, Karlovy Vary, Czech Republic, s.42-47. ISBN 978-1-4673-6134-7. V databáze: WOS. [1] 2016: WIELGUS, Andrzej - PLESKACZ, Witold. CMOS standard cells characterization for open defects for test pattern generation. In Proceedings of SPIE The International Society for Optical Engineering, 2016-01-01, 10175, pp. ISSN 0277786X. 
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